Ústav počítačových systémů

Vědecko-výzkumná činnost ústavu zahrnuje architekturu technických a programových prostředků vestavěných systémů, specifikaci a návrh systémů založených na počítačích, rekonfigurovatelné systémy, adaptivní systémy, diagnostiku a testování číslicových systémů a biologií inspirované výpočetní systémy.

Automatic design and optimization of digital circuits and programs according requested specification. For specific part of tasks we are able to achieve better results than it is possible by using standard development devices (for instance higher performance, lower circuits delay etc.). Theory and application of evolutionary algorithms for complicated optimization tasks, advanced evolutionary algorithms based on probabilistic models (EDA), utilization of graphic processors for implementation of parallel algorithms. Experience with development of new algorithms and hardware architectures which can be used in high performance networks and built-in devices. Development of new network devices according specifications and special requests.

Unique know-how of the given research unit:

  • Invention “Hardware Accelerator for Evolutionary Image Filters Design”
  • Invention “REPOMO32 - Reconfigurable polymorphic integrated circuit”
  • Tools for Cartesian Genetic Programming
  • Invention “Non-linear filter for (salt & pepper) impulse noise reduction in images”
  • Software “DNS-based White/Black/Grey-list”
  • Software “PyLDNS based tool for DNS configuration check”
  • REPOMOkit - universal evaluation platform for polymorphic electronics
  • REPOMO32 - Reconfigurable polymorphic integrated circuit
  • Methodologies of FT system design applicable in reconfigurable hardware

Thematic focus of the research unit / research team (research interests):

  • Evolvable hardware in a single FPGA
  • Development for evolvable hardware
  • Polymorphic electronics: REPOMO32 chip, synthesis of polymorphic circuits, applications
  • Theory and applications of evolvable components
  • Evolutionary design of innovative, testable, and fault-tolerant circuits
  • Theory and applications of virtual reconfigurable circuits
  • Real-world applications of evolvable hardware
  • Application-specific architectures (high-performance embedded
  • systems, multiprocessor systems on a chip, parallel performance prediction and tuning)
  • FPGA-based reconfigurable architectures (with application in gigabit networks, bioinformatics etc.)
  • Diagnostics, testability, and safety of digital systems
  • Bio-inspired hardware and applied evolutionary algorithms
  • Hardware acceleration of applications for biology data analysis (DNA sequences, proteins)
  • Advanced evolutionary algorithms applied to communication scheduling problems with respect to safety
  • Hardware acceleration of algorithms for monitoring network traffic and to increase traffic safety

Key research equipment:

  • Several powerful computer servers with LINUX operating system
  • GPU server for acceleration of evolutionary algorithm testing;
  • FPGA Xilinx; Oscilloscope Aggilent 7GHz
  • Logic analyzer Aggilent 1GHz others small devices for circuits;
  • Design software for FPGA Xilinx
  • Software for genetic programming and cartesian genetic programming; Software Mentor Graphics and Modeltech
  • NetCOPE platform for quick design of network application
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